`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/08/05 12:16:00
// Design Name: 
// Module Name: FeatureInBufferTest
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module FeatureInBufferTest;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter BANK = 4;
parameter DEPTH = 32;
//clk rst
logic clk;
logic rst;
//write
logic [DATA_WIDTH-1:0] wr_data;
logic [ADDR_WIDTH-1:0] wr_addr;
logic we;
//read
logic [ADDR_WIDTH-1:0] rd_addr;
logic [DATA_WIDTH-1:0] rd_data [0:BANK-1];
//write
logic [31:0] write_cnt;
logic start_write;
logic write_done;
logic writing;
//read
logic start_read;
logic read_done;
logic reading;
//clk
initial begin
  clk=0;
  forever begin
      #5 clk=~clk;
  end
end
//rst
initial begin
  rst=1;
  #20
  rst=0;
end
//
initial begin
  start_write=0;
  #100
  start_write=1;
  #10
  start_write=0;
end
//writing
always_ff@(posedge clk,posedge rst)
if(rst)
    writing<=0;
else if(start_write)
    writing<=1;
else if(write_done)
    writing<=0;
//write_done
assign write_done=(write_cnt==BANK*DEPTH-1)?1:0;
//write_cnt
always_ff@(posedge clk,posedge rst)
if(rst)
    write_cnt<=0;
else if(start_write)
    write_cnt<=0;
else if(writing)
    write_cnt<=write_cnt+1;  
//wr_data
always_comb
if(writing)
    wr_data=write_cnt;
else
    wr_data=0;
//wr_addr
always_comb
if(writing)
    wr_addr=write_cnt;
else
    wr_addr=0;
//we
assign we=writing;
//start_read
always_ff@(posedge clk)
if(write_done)
    start_read<=1;
else
    start_read<=0;
//reading
always_ff@(posedge clk,posedge rst)
if(rst)
    reading<=0;
else if(start_read)
    reading<=1;
else if(read_done)
    reading<=0;
//rd_addr
always_ff@(posedge clk)
if(start_read)
    rd_addr<=0;
else if(reading)
    rd_addr<=rd_addr+1;
//read_done
assign read_done=(rd_addr==DEPTH-1)?1:0;
//例化
FeatureInBuffer
#(.ADDR_WIDTH(ADDR_WIDTH),
  .DATA_WIDTH(DATA_WIDTH),
  .BANK(BANK),
  .DEPTH(DEPTH))
U (
.clk(clk),
.rst(rst),
//write input data
.wr_addr(wr_addr),
.wr_data(wr_data),
.we(we),
//read multi data
.rd_addr(rd_addr),
.rd_data(rd_data)
    );
endmodule
